CY7C1351 Description
The CY7C1351 is a 3.3V, 128K by 36 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351 is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle.
CY7C1351 Key Features
- Supports 66-MHz bus operations with zero wait states
- Data is transferred on every clock
- Internally self-timed output buffer control to eliminate the need to use OE
- Registered inputs for Flow-Through operation
- Byte Write capability
- 128K x 36 mon I/O architecture
- Single 3.3V power supply
- Fast clock-to-output times
- 11.0 ns (for 66-MHz device)
- 12.0 ns (for 50-MHz device)