3D3522 Datasheet | Data Delay Devices

FEATURES - - - - - - - - All-silicon, low-power CMOS technology 3.3V operation CMOS patible inputs and outputs Vapor phase, IR and wave solderable Auto-insertable (DIP pkg.) Low ground bounce noise Maximum data rate: 50 MBaud Data rate range: ±15% data 3 delay devices, inc. PACKAGES RX N/C N/C 1 2 3 4 5 6 7 14 13 12 11 10 9 8 N/C N/C N/C N/C N/C  RX CLK N/C GND 1 2 3 4 8 7 6 5 VDD N/C N/C DATB CLK N/C N/C GND DATB 3D3522M-xxx DIP (.300) 3D3522H-xxx Gull Wing (.300) 3D3522Z-xxx SOIC (.150) 3D3522-xxx DIP (.300) 3D3522G-xxx Gull Wing (.300) 3D3522D-xxx SOIC (.150) For mechanical dimensions, click here. For package marking details, click here. FUNCTIONAL DESCRIPTION PIN DESCRIPTIONS .. The 3D3522 product family consists of monolithic CMOS Manchester RX Signal Input Decoders. The unit accepts at the RX input a bi-phase-level, CLK Signal Output (Clock) embedded-clock signal. In this encoding mode, a logic one is DATB Signal Output (Data) represented by a high-to-low transition within the bit cell, while a logic VDD +3.3 Volts zero is represented by a low-to-high transition. The recovered clock GND Ground and data signals are presented on CLK and DATB, respectively, with the data signal inverted. The operating baud rate (in MBaud) is specified by the dash number. The input baud rate may vary by as much as ±15% from the nominal device baud rate without promising the integrity of the information received. Because the 3D3522 is not PLL-based, it does not require a long preamble in order to lock onto the received signal. Rather, the device requires at most one bit cell before the data presented at the output is valid. This is extremely useful in cases where the information arrives in bursts and the input is otherwise turned off. The all-CMOS 3D3522 integrated circuit has been designed as a reliable, economic alternative to hybrid Manchester Decoders. It is CMOS-patible and is offered in standard 8-pin and 14-pin auto-insertable DIPs and space saving...