74AUP2G07 Overview
The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP2G07 is posed of two buffers with open drain outputs designed for operation over a power supply range of 0.8V to 3.6V. The device is fully specified for partial power down applications using IOFF.
74AUP2G07 Key Features
- Advanced Ultra Low Power (AUP) CMOS
- Supply Voltage Range from 0.8V to 3.6V
- 4mA Output Drive at 3.0V
- Low Static Power Consumption
- ICC < 0.9µA
- Low Dynamic Power Consumption
- CPD = 1.2pF Typical at 3.6V
- IOFF Supports Partial-Power-Down Mode Operation
- ESD Protection per JESD 22
- Exceeds 200-V Machine Model (A115)
