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74AUP2G34 - DUAL BUFFERS

General Description

The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications.

The 74AUP2G34 is composed of two buffers with standard push-pull outputs designed for operation over a power supply range of 0.8V to 3.6V.

Key Features

  • Advanced Ultra Low Power (AUP) CMOS.
  • Supply Voltage Range from 0.8V to 3.6V.
  • ±4mA Output Drive at 3.0V.
  • Low Static Power Consumption.
  • ICC < 0.9µA.
  • Low Dynamic Power Consumption.
  • CPD = 6pF Typical at 3.6V.
  • Schmitt Trigger Action at All Inputs Make the Circuit Tolerant for Slower Input Rise and Fall Time. The Hysteresis is Typically 250mV at VCC = 3.0V.
  • IOFF Supports Partial-Power-Down Mode Operation.
  • ESD Protection per JESD 22.
  • Exceeds 200-V.

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The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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ADAVDAVANCNECDE ID INFNFORORMAMTAITIOONN 74AUP2G34 DUAL BUFFERS Description The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP2G34 is composed of two buffers with standard push-pull outputs designed for operation over a power supply range of 0.8V to 3.6V. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow when the device is powered down. The gates perform the positive Boolean function: YA Features  Advanced Ultra Low Power (AUP) CMOS  Supply Voltage Range from 0.8V to 3.6V  ±4mA Output Drive at 3.0V  Low Static Power Consumption  ICC < 0.