74AUP2G38 Datasheet | NXP Semiconductors

.. Low-power dual 2-input NAND gate (open-drain) Rev. 01 - 16 October 2006 Product data sheet 1. General description The 74AUP2G38 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS patible TTL families. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging...