EDI8L32256C Datasheet | EDI

Features 256Kx32 bit CMOS Static DSP Memory Solution - Texas Instruments TMS320C3x, TMS320C4x - Analog SHARCTM DSP - Motorola DSP96002 Random Access Memory Array - Fast Access Times: 15, 17, 20 and 25ns - Individual Byte Enables - User Configurable Organization with Minimal Additional Logic - Master Output Enable and Write Control - TTL patible Inputs and Outputs - Fully Static, No Clocks Surface Mount Package - 68 Lead PLCC, No. 99, JEDEC MO-47AE - Small Footprint, 0.990 Sq. In. - Multiple Ground Pins for Maximum Noise Immunity Single +5V (±5%) Supply Operation The EDI8L32256C is a high speed, 5V, 8 megabit SRAM. The device is available with access times of 15, 17, 20 and 25ns, allowing the creation of a no wait state DSP memory solution. The device can be configured as a 256Kx32 and used to create a single chip external data memory solution for Texas Instruments' TMS320C30/31, TMS 320C32 or TMS320C4x, Motorola's DSP96002 and Analog Device's SHARCTM DSP. Alternatively the device's chip enables can be used to configure it as a 512Kx16. A 512Kx48 program memory array for Analog's SHARCTM DSP is created using three devices. If this memory is too deep, two 256Kx24s (EDI8L24256C) can be used to create a 256Kx48 array or two 128Kx24s (EDI8L24128C) can be used to create a 128Kx48 array. The device provides a 32% space savings when pared to two monolithic 256Kx16, 44 pin SOJs. The device provides a memory upgrade of the EDI8L32128C (128Kx32) and the EDI8L3265C (64Kx32). For more memory the device can be upgraded to the EDI8L32512C (512Kx32). NOTE: Solder Reflow temperature should not exceed 260°C for 10 seconds. Pin Configurations and Block Diagram DQ16 NC A17 BS3 BS2 BS1 BSØ E1 VCC NC EØ G W A16 A15 A14 DQ15 Pin Names 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 VCC DQ7 DQ6 DQ5 DQ4 VSS DQ3 DQ2 DQ1 DQ17 DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 VCC DQ24 DQ25 DQ26 DQ27 VSS DQ28 DQ29 DQ30 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25...