F50L4G41XB Datasheet | Elite Semiconductor Microelectronics Technology

FEATURES - Single-level cell (SLC) technology - Organization - Page size ×1: 4352 bytes (4096 + 256 bytes) - Block size: 64 pages (256K + 16K bytes) - Plane size: 1 × 2048 blocks - Standard and extended SPI-patible serial bus interface - Instruction, address on 1 pin; data out on 1, 2, or 4 pins - Instruction on 1 pin; address, data out on 2 or 4 pins - Instruction, address on 1 pin; data in on 1 or 4 pins - Continuous read within block, configure-able by feature register - User-selectable internal ECC supported - 8 bits/sector - Array performance - 104 MHz clock frequency (MAX) - Page read: 25μs (MAX) with on-die ECC disabled; 115μs (MAX) with on-die ECC enabled - Page program: 200μs (TYP) with on-die ECC disabled; 240μs (TYP) with on-die ECC enabled - Block erase: 2ms (TYP) - Advanced features - Read page cache mode (x2, x4, Dual, Quad, and Random) - Read unique ID - Read parameter page - Device initialization - Automatic device initialization after power-up - Security - Block 0 is valid when shipped from factory with ECC enabled - Software write protection with lock register - Hardware write protection to freeze BP bits - Lock tight to freeze BP bits during one power cycle - Permanent block lock protection - OTP Space: 10 pages one-time programmable NAND Flash memory area - Quality and reliability - Endurance: 100,000 PROGRAM/ERASE cycles - Data retention: JESD47H-pliant; see qualification report - Additional: Uncycled data retention: 10 years 24/7 @ 70°C - Operating voltage range - VCC = 2.7- 3.6V - Operating temperature - mercial: 0°C to +70°C ORDERING...