F59L1G81MB
Description
The device is a 128Mx8bit with spare 4Mx8bit capacity.
Key Features
- Voltage Supply: 3.3V (2.7V~3.6V)
- Organization
- Memory Cell Array: (128M + 4M) x 8bit - Data Register: (2K + 64) x 8bit
- Automatic Program and Erase - Page Program: (2K + 64) Byte - Block Erase: (128K + 4K) Byte
- Page Read Operation - Page Size: (2K + 64) Byte - Random Read: 25us (Max.) - Serial Access: 25ns (Min.) (3.3V)
- Memory Cell: 1bit/Memory Cell
- Fast Write Cycle Time - Program time: 300us - typical - Block Erase time: 4ms - typical
- mand/Address/Data Multiplexed I/O Port
- Hardware Data Protection - Program/Erase Lockout During Power Transitions
- Reliable CMOS Floating Gate Technology - ECC Requirement: - 4bit/528Byte - Endurance: 100K Program/Erase cycles - Data Retention: 10 years
