M12L128324A-6BG2E Datasheet | Elite Semiconductor Microelectronics Technology

Features JEDEC standard 3.3V power supply LVTTL patible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency (2 & 3) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock DQM for masking Auto & self refresh 64ms refresh period (4K cycle) M12L128324A (2E) 1M x 32 Bit x 4 Banks Synchronous DRAM ORDERING INFORMATION Product ID M12L128324A-5BG2E M12L128324A-6BG2E M12L128324A-7BG2E Max Freq. 200MHz Package 90 FBGA ments Pb-free 166MHz 90 FBGA Pb-free 143MHz 90 FBGA Pb-free GENERAL DESCRIPTION The M12L128324A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. BALL CONFIGURATION (TOP VIEW) (BGA90, 8mm X13mm X1mm Body, 0.8mm Ball Pitch) 3 456 A DQ26 DQ24 VSS VDD DQ23 DQ21 B DQ28 VDDQ VSSQ VDDQ VSSQ DQ19 C VSSQ DQ27 DQ25 DQ22 DQ20 VDDQ D VSSQ DQ29 DQ30 DQ17 DQ18 VDDQ E VDDQ DQ31 NC NC DQ16 VSSQ F VSS DQM3 A3 A2 DQM2 VDD G A4 A5 A6 A10/AP A0 A1 H A7 A8 NC NC BA1 A11 J CLK CKE A9 BA0 CS RAS K DQM1 NC NC CAS WE DQM0 L VDDQ DQ8...