M12L16161A-5TG2R Overview
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Burst Read Single-bit Write operation DQM for masking ORDERING INFORMATION Auto & self...
M12L16161A-5TG2R Key Features
- JEDEC standard 3.3V power supply
- LVTTL patible with multiplexed address
- Dual banks operation
- MRS cycle with address key programs
- CAS Latency (2 & 3 )
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
- All inputs are sampled at the positive going edge of the system clock