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ESMT
SDRAM
M12L16161A (2R)
512K x 16Bit x 2Banks Synchronous DRAM
FEATURES
GENERAL DESCRIPTION
JEDEC standard 3.3V power supply
The M12L16161A is 16,777,216 bits synchronous high data
LVTTL compatible with multiplexed address
rate Dynamic RAM organized as 2 x 524,288 words by 16 bits,
Dual banks operation MRS cycle with address key programs
fabricated with high performance CMOS technology. Synchronous design allows precise cycle control with the use
- CAS Latency (2 & 3 )
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the
of system clock I/O transactions are possible on every clock cycle.
M12L16161A-5TG2R Datasheet
