M12L16161A-7TIG2Q Overview
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. z Burst Read Single-bit Write operation z DQM.
M12L16161A-7TIG2Q Key Features
- CAS Latency (2 & 3 )
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave) z All inputs are sampled at the positive going edge of the system clock