Datasheet4U Logo Datasheet4U.com

M14D128168A - 2M x 16 Bit x 4 Banks DDR II SDRAM

General Description

Pin Name A0~A12, BA0,BA1 DQ0~DQ15 RAS CAS WE VSS VDD DQS, DQS (LDQS, LDQS UDQS, UDQS ) ODT NC Function Address inputs - Row address A0~A11 - Column address A0~A8 A12: use for MRS/EMRS A10/AP : Auto Precharge BA0, BA1 : Bank selects (4 Banks) Data-in/Data-out Command input Command input Command inp

Key Features

  • JEDEC Standard.
  • VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V.
  • Internal pipelined double-data-rate architecture; two data access per clock cycle.
  • Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.
  • On-chip DLL.
  • Differential clock inputs (CLK and CLK ).
  • DLL aligns DQ and DQS transition with CLK transition.
  • 1KB page size - Row address: A0 to A11 - Column address: A0 to A8.
  • Quad bank operation.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
M140NWR1-R0 TFT LCD IVO
M140NWR2-R0 TFT LCD IVO
M140NWR2-R1 TFT LCD IVO
M140NWR2-R2 TFT LCD IVO
M141-X76C TFT Color LCD IMES

Other Datasheets by ESMT (Elite Semiconductor Microelectronics Technology)

Part Number Description
M14D128168A-1.5BG2Y 2M x 16 Bit x 4 Banks DDR II SDRAM
M14D128168A-1.6BG2Y 2M x 16 Bit x 4 Banks DDR II SDRAM
M14D128168A-1.8BG2Y 2M x 16 Bit x 4 Banks DDR II SDRAM
M14D128168A-2.5BG2Y 2M x 16 Bit x 4 Banks DDR II SDRAM
M14D1G1664A 8M x 16 Bit x 8 Banks DDR II SDRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
ESMT DDR II SDRAM M14D128168A (2Y) 2M x 16 Bit x 4 Banks DDR II SDRAM Features  JEDEC Standard  VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V  Internal pipelined double-data-rate architecture; two data access per clock cycle  Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.