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M14F5121632A Description

Pin Name A0~A12, BA0,BA1 DQ0~DQ15 RAS CAS WE VSS VDD DQS, DQS (LDQS, LDQS UDQS, UDQS) ODT NC Function Address inputs - Row address A0~A12 - Column.

M14F5121632A Key Features

  • JEDEC Standard
  • VDD / VDDQ = 1.55V ± 0.075V
  • Internal pipelined double-data-rate architecture; two data access per clock cycle
  • Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation
  • On-chip DLL
  • Differential clock inputs (CLK and CLK )
  • DLL aligns DQ and DQS transition with CLK transition
  • Quad bank operation
  • CAS Latency : 3, 4, 5, 6, 7, 8
  • Additive Latency: 0, 1, 2, 3, 4, 5, 6, 7