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M14F5121632A - DDR II SDRAM

Datasheet Summary

Description

Pin Name A0~A12, BA0,BA1 DQ0~DQ15 RAS CAS WE VSS VDD DQS, DQS (LDQS, LDQS UDQS, UDQS) ODT NC Function Address inputs - Row address A0~A12 - Column address A0~A9 A10/AP : Auto Precharge BA0, BA1 : Bank selects (4 Banks) Data-in/Data-out Command input Command input Command input Ground Power Pin Na

Features

  • JEDEC Standard.
  • VDD / VDDQ = 1.55V ± 0.075V.
  • Internal pipelined double-data-rate architecture; two data access per clock cycle.
  • Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.
  • On-chip DLL.
  • Differential clock inputs (CLK and CLK ).
  • DLL aligns DQ and DQS transition with CLK transition.
  • Quad bank operation.
  • CAS Latency : 3, 4, 5, 6, 7, 8.
  • Additive Latency: 0, 1, 2, 3, 4, 5, 6, 7.

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Datasheet Details

Part number M14F5121632A
Manufacturer ESMT
File Size 1.95 MB
Description DDR II SDRAM
Datasheet download datasheet M14F5121632A Datasheet
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ESMT M14F5121632A (2A) DDR II SDRAM 8M x 16 Bit x 4 Banks DDR II SDRAM Features  JEDEC Standard  VDD / VDDQ = 1.55V ± 0.075V  Internal pipelined double-data-rate architecture; two data access per clock cycle  Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.
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