M14F5121632A Overview
Key Features
- JEDEC Standard
- VDD / VDDQ = 1.55V ± 0.075V
- Internal pipelined double-data-rate architecture; two data access per clock cycle
- Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation
- Differential clock inputs (CLK and CLK )
