Datasheet4U Logo Datasheet4U.com

M15T2G8256A-BDBG2L Datasheet 32m X 8 Bit X 8 Banks Ddr3 Sdram

Manufacturer: ESMT (Elite Semiconductor Microelectronics Technology)

Overview: ESMT DDR3(L) SDRAM Feature  Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V) ˗ SSTL_135: VDD/VDDQ = 1.35V(-0.067V/+0.1V)  JEDEC DDR3(L) Compliant ˗ 8n Prefetch Architecture ˗ Differential Clock (CK/ CK ) and Data Strobe (DQS/ DQS ) ˗ Double-data rate on DQs, DQS and DM  Data Integrity ˗ Auto Self Refresh (ASR) by DRAM built-in TS ˗ Auto Refresh and Self Refresh Modes  Power Saving Mode ˗ Power Down Mode  Signal Integrity ˗ Configurable DS for system compatibility ˗ Configurable On-Die Termination ˗ ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%) M15T2G8256A (2L) 32M x 8 Bit x 8 Banks DDR3(L) SDRAM  Signal Synchronization 1 ˗ Write Leveling via MR settings ˗ Read Leveling via MPR  Programmable Functions ˗ CAS Latency (5/6/7/8/9/10/11/13) ˗ CAS Write Latency (5/6/7/8/9) ˗ Additive Latency (0/CL-1/CL-2) ˗ Write Recovery Time (5/6/7/8/10/12/14/16) ˗ Burst Type (Sequential/Interleaved) ˗ Burst Length (BL8/BC4/BC4 or 8 on the fly) ˗ Self Refresh Temperature Range(Normal/Extended) ˗ Output Driver Impedance (34/40) ˗ On-Die Termination of Rtt_Nom(20/30/40/60/120) ˗ On-Die Termination of Rtt_WR(60/120) ˗ Precharge Power Down (slow/fast) Note: 1. Only Support prime DQ’s feedback for each byte lane. Ordering Information Product ID M15T2G8256A–DEBG2L M15T2G8256A–BDBG2L Max Freq. VDD Data Rate (CL-tRCD-tRP) Package 933MHz 1.35/ 1.5V DDR3(L)-1866 (13-13-13) 800MHz 1.35/ 1.5V DDR3(L)-1600 (11-11-11) 78 ball BGA Comments Pb-free Pb-free Elite Semiconductor Memory Technology Inc Publication Date : Aug. 2018 Revision : 1.

This datasheet includes multiple variants, all published together in a single manufacturer document.

General Description

The 2Gb Double-Data-Rate-3(L) (DDR3(L)) DRAM is double data rate architecture to achieve high-speed operation.

It is internally configured as an eight bank DRAMs.

The 2Gb chip is organized as 32Mbit x 8 I/Os x 8 bank devices.

Key Features

  • and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion. These devices operate with a single 1.35V -0.067V/+0.1V or 1.5V ± 0.075V power supply and are available in BGA packages. DDR3(L) SDRAM Addressing Configuration 256Mb x 8 # of Bank 8.

More Datasheets from ESMT (Elite Semiconductor Microelectronics Technology)

Part Number Description
M15T2G8256A-BDBG2R 32M x 8 Bit x 8 Banks DDR3 SDRAM
M15T2G8256A-DEBG2L 32M x 8 Bit x 8 Banks DDR3 SDRAM
M15T2G8256A-DEBG2R 32M x 8 Bit x 8 Banks DDR3 SDRAM
M15T2G8256A-EFBG2R 32M x 8 Bit x 8 Banks DDR3 SDRAM
M15T2G8256A 32M x 8 Bit x 8 Banks DDR3 SDRAM
M15T2G16128A 16M x 16 Bit x 8 Banks DDR3 SDRAM
M15T2G16128A-BDBG2L 16M x 16 Bit x 8 Banks DDR3 SDRAM
M15T2G16128A-BDBG2LS 16M x 16 Bit x 8 Banks DDR3 SDRAM
M15T2G16128A-BDBG2P 16M x 16 Bit x 8 Banks DDR3 SDRAM
M15T2G16128A-BDBG2R 16M x 16 Bit x 8 Banks DDR3 SDRAM

M15T2G8256A-BDBG2L Distributor