Datasheet Details
| Part number | M15T2G8256A-DEBG2L |
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| Manufacturer | ESMT (Elite Semiconductor Microelectronics Technology) |
| File Size | 3.83 MB |
| Description | 32M x 8 Bit x 8 Banks DDR3 SDRAM |
| Datasheet |
 M15T2G8256A-DEBG2L Datasheet
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General Description
The 2Gb Double-Data-Rate-3(L) (DDR3(L)) DRAM is double data rate architecture to achieve high-speed operation.
It is internally configured as an eight bank DRAMs.
The 2Gb chip is organized as 32Mbit x 8 I/Os x 8 bank devices.
Key Features
- and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion. These devices operate with a single 1.35V -0.067V/+0.1V or 1.5V ± 0.075V power supply and are available in BGA packages. DDR3(L) SDRAM Addressing Configuration 256Mb x 8 # of Bank 8.