M52D5121632A Description
The M52D5121632A is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by 16 bits. Synchronous design allows precise.
M52D5121632A Key Features
- CAS Latency (2, 3)
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave) EMRS cycle with address All inputs are sampled at the positive going edge of the sy
- PASR (Partial Array Self Refresh)
- TCSR (Temperature pensated Self Refresh)
- DS (Driver Strength)
- Deep Power Down (DPD) Mode DQM for masking Auto & self refresh 64ms refresh period (8K cycle)