M13S256328A Datasheet PDF (2M x 32 Bit x 4 Banks Double Data Rate SDRAM) | Download Elite Semiconductor Memory Technology M13S256328A

M13S256328A - 2M x 32 Bit x 4 Banks Double Data Rate SDRAM

Description

Pin Name Function Address inputs - Row address A0~A11 - Column address A0~A7, A9 A8/AP : AUTO Precharge BA0, BA1 : Bank selects (4 Banks) Data-in/Data-out Row address strobe Column address strobe Write enable Ground Power Bi- directional Data Strobe.

Features

z z z z z z z z z z z z z z z z z z z z z M13S256328A 2M x 32 Bit x 4 Banks Double Data Rate SDRAM JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) On-chip DLL Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition Quad bank operation CAS Latency : 2; 2.5; 3 Burst Type : Sequential and Interleave Burst Length : 2, 4, 8, full page Full page burst length for sequential burst ty.

Datasheet Details

Part number	M13S256328A
Manufacturer	Elite Semiconductor Memory Technology
File Size	856.85 KB
Description	2M x 32 Bit x 4 Banks Double Data Rate SDRAM
Datasheet	M13S256328A Datasheet

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Full PDF Text Transcription

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www.DataSheet4U.com ESMT DDR SDRAM Features z z z z z z z z z z z z z z z z z z z z z M13S256328A 2M x 32 Bit x 4 Banks Double Data Rate SDRAM JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) On-chip DLL Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition Quad bank operation CAS Latency : 2; 2.

Published: Sep 17, 2009 |