M13S32321A Datasheet | Elite Semiconductor Memory Technology

.. ESMT DDR SDRAM Features z z z z z z z z z z z z z z z z z z z 256K x 32 Bit x 4 Banks Double Data Rate SDRAM JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) On-chip DLL Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition Quad bank operation CAS Latency : 3; 4 Burst Type : Sequential and Interleave Burst Length : 2, 4, 8 All inputs except data & DM are sampled at the rising edge of the system clock(CLK) Data I/O transitions on both edges of data strobe (DQS) DQS is edge-aligned with data for reads; center-aligned with data for WRITE Data mask (DM) for write masking only VDD = 2.375V ~ 2.625V, VDDQ = 2.375V ~ 2.625V Auto & Self refresh 32ms refresh period (4K cycle) SSTL-2 I/O interface 100pin LQFP package Operating Frequencies : PRODUCT NO. M13S32321A -5L MAX FREQ 200MHz VDD 2.5V PACKAGE 100 LQFP M13S32321A -6L 166MHz 2.5V 100 LQFP Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2006 Revision : 1.0 1/49 .. ESMT Functional Block Diagram CLK CLK CKE Address Mode Register & Extended Mode Register Clock Generator Bank D Bank C Bank B Row Decoder Row Address Buffer & Refresh Counter Bank A Sense Amplifier mand Decoder Control Logic CS RAS CAS WE Data Control Circuit Input & Output Buffer Latch Circuit Column Address Buffer & Refresh Counter Column Decoder CLK,...