M13S32321A Datasheet PDF (256K x 32 Bit x 4 Banks Double Data Rate SDRAM) | Download Elite Semiconductor Memory Technology M13S32321A

M13S32321A - 256K x 32 Bit x 4 Banks Double Data Rate SDRAM

Description

Pin Name Function Address inputs - Row address A0~A9 - Column address A0~A7 A8/AP : AUTO Precharge BA0, BA1 : Bank selects (4 Banks) Data-in/Data-out Row address strobe Column address strobe Write enable Ground Power Bi- directional Data Strolle.

Features

z z z z z z z z z z z z z z z z z z z M13S32321A 256K x 32 Bit x 4 Banks Double Data Rate SDRAM JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) On-chip DLL Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition Quad bank operation CAS Latency : 3; 4 Burst Type : Sequential and Interleave Burst Length : 2, 4, 8 All inputs except data & DM are sampled at the rising edge of the.

Datasheet Details

Part number	M13S32321A
Manufacturer	Elite Semiconductor Memory Technology
File Size	825.46 KB
Description	256K x 32 Bit x 4 Banks Double Data Rate SDRAM
Datasheet	M13S32321A Datasheet

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Full PDF Text Transcription

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www.DataSheet4U.com ESMT DDR SDRAM Features z z z z z z z z z z z z z z z z z z z M13S32321A 256K x 32 Bit x 4 Banks Double Data Rate SDRAM JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) On-chip DLL Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition Quad bank operation CAS Latency : 3; 4 Burst Type : Sequential and Interleave Burst Length : 2, 4, 8 All inputs except data & DM are sampled at the rising edge of the system clock(CLK) Data I/O transitions on both edges of data strobe (DQS) DQS is edge-aligned with data for reads; center-aligned with data for WRITE Data mask (DM) for write masking only VDD = 2.375V ~ 2.625V, VDDQ = 2.375V ~ 2.

Published: Sep 17, 2009 |