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EDD2516AETA Datasheet

(edd2508aeta / Edd2516aeta) 256m Bits Ddr Sdram

Manufacturer: Elpida Memory

This datasheet includes multiple variants, all published together in a single manufacturer document.

EDD2516AETA Overview

DATA SHEET 256M bits DDR SDRAM EDD2508AETA (32M words × 8 bits) EDD2516AETA (16M words × 16 bits) Specifications Density: 256M bits Organization  8M words × 8 bits × 4 banks (EDD2508AETA) ..  4M words × 16 bits × 4 banks (EDD2516AETA) Package:.

EDD2516AETA Key Features

  • Double-data-rate architecture; two data transfers per clock cycle
  • The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture
  • Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver
  • Data inputs, outputs, and DM are synchronized with DQS
  • DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
  • Differential clock inputs (CK and /CK)
  • DLL aligns DQ and DQS transitions with CK transitions
  • mands entered on each positive CK edge; data and data mask referenced to both edges of DQS
  • Data mask (DM) for write data

EDD2516AETA Distributor