EDD2516AKTA-E - 256M bits DDR SDRAM (16M words x16 bits DDR400)

Description

The EDD2516AKTA is a 256M bits Double Data Rate (DDR) SDRAM organized as 4,194,304 words × 16 bits × 4 banks.

Read and write operations are performed at the cross points of the CK and the /CK.

This highspeed data transfer is realized by the 2 bits prefetchpipelined architecture.

Features

Power supply : VDDQ = 2.5V ± 0.2V : VDD = 2.5V ± 0.2V.
Data rate: 333Mbps/266Mbps (max. ).
Double Data Rate architecture; two data transfers per clock cycle.
Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver.
Data inputs, outputs, and DM are synchronized with DQS.
4 internal banks for concurrent operation.
DQS is edge aligned with data for READs; center aligned with dat.

Elpida Memory

📥 Download Datasheet

Datasheet Details

Part number	EDD2516AKTA-E
Manufacturer	Elpida Memory
File Size	606.56 KB
Description	256M bits DDR SDRAM (16M words x16 bits DDR400)
Datasheet	EDD2516AKTA-E Datasheet
Additional preview pages of the EDD2516AKTA-E datasheet.

📁 Similar Datasheet

EDD11 - Doppelendtriode (TELEFUNKEN)

Other Datasheets by Elpida Memory

EDD2516AKTA-5-E - 256M bits DDR SDRAM (16M words x16 bits DDR400)
EDD2516AETA - (EDD2508AETA / EDD2516AETA) 256M bits DDR SDRAM
EDD2504AKTA - 256M bits DDR SDRAM (64M words x 4 bits)
EDD2504AKTA - 256M bits DDR SDRAM (64M words x 4 bits)
EDD2504AKTA-E - 256M bits DDR SDRAM (64M words x 4 bits)
EDD2504AKTA-E - 256M bits DDR SDRAM (64M words x 4 bits)
EDD2508AETA - (EDD2508AETA / EDD2516AETA) 256M bits DDR SDRAM
EDD2508AKTA-5 - 256M bits DDR SDRAM (32M words x 8 bits DDR400)

Full PDF Text Transcription

Click to expand full text

( DataSheet : www.DataSheet4U.com ) DATA SHEET 256M bits DDR SDRAM EDD2516AKTA-E (16M words × 16 bits) Description The EDD2516AKTA is a 256M bits Double Data Rate (DDR) SDRAM organized as 4,194,304 words × 16 bits × 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This highspeed data transfer is realized by the 2 bits prefetchpipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. It is packaged in 66-pin plastic TSOP (II). Pin Configurations /xxx indicates active low signal.

Published: May 7, 2006 |