Datasheet Summary
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DATA SHEET
1G bits DDR2 SDRAM
EDE1104AASE (256M words × 4 bits) EDE1108AASE (128M words × 8 bits)
Description
The EDE1104AASE is a 1G bits DDR2 SDRAM organized as 33,554,432 words × 4 bits × 8 banks. The EDE1108AASE is a 1G bits DDR2 SDRAM organized as 16,777,216 words × 8 bits × 8 banks. They are packaged in 68-ball FBGA (µBGA) package.
Features
- Power supply: VDD, VDDQ = 1.8V ± 0.1V
- Double-data-rate architecture: two data transfers per clock cycle
- Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data, to be used in capturing data at the receiver
- DQS is edge aligned with data for READs: centeraligned with data for WRITEs
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