EDE1108AJBG Overview
DATA SHEET 1G bits DDR2 SDRAM EDE1108AJBG (128M words × 8 bits) EDE1116AJBG (64M words × 16 bits) Specifications Density: VDD, VDDQ = 1.8V ± 0.1V Data rate 800Mbps (max.) 1KB page size (EDE1108AJBG) Row address: A0 to A13 Column address:.
EDE1108AJBG Key Features
- Double-data-rate architecture; two data transfers per clock cycle
- The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
- Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the recei
- DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
- Differential clock inputs (CK and /CK)
- DLL aligns DQ and DQS transitions with CK transitions
- mands entered on each positive CK edge; data and data mask referenced to both edges of DQS
- Data mask (DM) for write data
- Posted /CAS by programmable additive latency for better mand and data bus efficiency
- Programmable RDQS, /RDQS output for making × 8 organization patible to × 4 organization