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EDE1108AJBG - 1G bits DDR2 SDRAM

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Elpida Memory

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EDE1108AJBG 1G bits DDR2 SDRAM by Elpida Memory - Datasheet Preview — Datasheet preview – EDE1108AJBG

Datasheet Details

Part number	EDE1108AJBG
Manufacturer	Elpida Memory
File Size	537.89 KB
Description	1G bits DDR2 SDRAM
Datasheet	EDE1108AJBG Datasheet
Additional preview pages of the EDE1108AJBG datasheet.

Product details

Features

Double-data-rate architecture; two data transfers per clock cycle.
The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture.
Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver.
DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
Differential clock inputs (CK and /CK).
DLL aligns DQ and DQS transitions with CK transi.

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Published: Oct 13, 2014 |