EM63B165 Datasheet | Etron Technology

Features - Fast access time from clock: 5/5.4/6 ns - Fast clock rate: 200/166/143 MHz - Fully synchronous operation - Internal pipelined architecture - 8M word x 16-bit x 4-bank - Programmable Mode registers - CAS Latency: 2 or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: Sequential or Interleaved - Burst stop function - Auto Refresh and Self Refresh - 8192 refresh cycles/64ms - CKE power down mode - Single +3.3V ±0.3V power supply - Operating Temperature: TA = -40~85°C (Industrial) - Interface: LVTTL - Package: (Pb free and Halogen free) - 54-pin 400 mil plastic TSOP II package - 54-ball 8 x 8 x 1.2mm (max) FBGA package Overview The EM63B165 SDRAM is a high-speed CMOS synchronous DRAM containing 512 Mbits. It is internally configured as 4 Banks of 8M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a Bank Activate mand which is then followed by a Read or Write mand. The EM63B165 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications. Table 1. Key Specifications -5I t CK3 Clock Cycle time(min.) 5 t AC3 Access time from CLK (max.) 5 t RAS Row Active time(min.) 40 t RC Row Cycle time(min.) Table 2. Ordering Information Part Number Frequency EM63B...