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EM68932DVKB - 4M x 32 Mobile DDR Synchronous DRAM

General Description

Table 2.

Differential Clock: CK and CK are differential clock inputs.

All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK .

Key Features

  • Fast clock rate: 166/133 MHz Differential Clock CK & CK Bi-directional DQS Four internal banks, 1M x 32-bit for each bank Edge-aligned with read data, centered in write data Programmable Mode and Extended Mode Registers - CAS Latency: 2, or 3 - Burst length: 2, 4, or 8 - Burst Type: Sequential & Interleaved - PASR (Partial Array Self Refresh) - Auto TCSR (Temperature Compensated Self Refresh) - DS (Drive Strength).
  • Individual byte writes mask control.
  • DM Write Latency = 0.

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Other Datasheets by Etron Technology

Part Number Description
EM68932DVKA 4M x 32 Mobile DDR Synchronous DRAM
EM68916CWQA 8M x 16 bit DDRII Synchronous DRAM
EM68916DVAA 8M x 16 Mobile DDR Synchronous DRAM
EM68A16CBQC 16M x 16 bit DDRII Synchronous DRAM
EM68B08CWAH 64M x 8 bit DDRII Synchronous DRAM

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www.DataSheet.co.kr EtronTech Etron Confidential Features Fast clock rate: 166/133 MHz Differential Clock CK & CK Bi-directional DQS Four internal banks, 1M x 32-bit for each bank Edge-aligned with read data, centered in write data Programmable Mode and Extended Mode Registers - CAS Latency: 2, or 3 - Burst length: 2, 4, or 8 - Burst Type: Sequential & Interleaved - PASR (Partial Array Self Refresh) - Auto TCSR (Temperature Compensated Self Refresh) - DS (Drive Strength) • Individual byte writes mask control • DM Write Latency = 0 • Precharge Standby Current = 100 µA • Self Refresh Current = 200 µA • Deep power-down Current = 10 µA max. at 85℃ • Auto Refresh and Self Refresh • 4096 refresh cycles / 64ms • No DLL (Delay Lock Loop), to reduce power; CK to DQS is not synchronized.