EM6A8160TSD Datasheet PDF (4M x 16 bit DDR Synchronous DRAM)

EM6A8160TSD - 4M x 16 bit DDR Synchronous DRAM

Description

Table 2.

Input Differential Clock: CK, CK are driven by the system clock.

All SDRAM input signals are sampled on the positive edge of CK.

Features

Fast clock rate: 250/200MHz.
Differential Clock CK & CK.
Bi-directional DQS.
DLL enable/disable by EMRS.
Fully synchronous operation.
Internal pipeline architecture.
Four internal banks, 1M x 16-bit for each bank.
Programmable Mode and Extended Mode registers - CAS Latency: 2, 2.5, 3, 4 - Burst length: 2, 4, 8 - Burst Type: Sequential & Interleaved.
Individual byte write mask control.
DM Write Latency = 0.
Auto Refresh and Self Refresh.

Datasheet Details

Part number	EM6A8160TSD
Manufacturer	Etron Technology
File Size	732.35 KB
Description	4M x 16 bit DDR Synchronous DRAM
Datasheet	EM6A8160TSD Datasheet
Additional preview pages of the EM6A8160TSD datasheet.

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Full PDF Text Transcription

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EtronTech EM6A8160TSD 4M x 16 bit DDR Synchronous DRAM (SDRAM) Advance (Rev. 1.2, Nov. /2023) Features  Fast clock rate: 250/200MHz  Differential Clock CK & CK  Bi-directional DQS  DLL enable/disable by EMRS  Fully synchronous operation  Internal pipeline architecture  Four internal banks, 1M x 16-bit for each bank  Programmable Mode and Extended Mode registers - CAS Latency: 2, 2.5, 3, 4 - Burst length: 2, 4, 8 - Burst Type: Sequential & Interleaved  Individual byte write mask control  DM Write Latency = 0  Auto Refresh and Self Refresh  4096 refresh cycles / 64ms  Precharge & active power down  Operating Temperature: TA = 0~70°C (Commercial)  Power supplies: VDD & VDDQ = 2.5V  0.2V  Interface: SSTL_2 I/O Interface  Package: 66 Pin TSOP II, 0.

Published: Nov 24, 2024 |