EM6AA320 Description
EtronTech Revision History Revision 0.6(May, 2006) Preliminary Spec Delete confidential wording. EM6AA320 Revision 0.5(May, 2003) Preliminary Spec Revised the AC Timing of tCLK at CL=4 for pure VDD/VDDQ=2.8V spec. Revision 0.4(May, 2003) Preliminary Spec Revised the AC Timing of tCLK at CL=4 for pure VDD/VDDQ=2.5V spec.
EM6AA320 Key Features
- Fast clock rate: 300/275/250/200 MHz
- Differential Clock CK & CK# input
- 4 Bi-directional DQS. Data transactions on both edges of DQS (1DQS / Byte)
- DLL aligns DQ and DQS transitions
- Edge aligned data & DQS output
- Center aligned data & DQS input
- 4 banks operation
- Programmable mode and extended mode registers
- CAS# Latency: 3, 4, 5
- Burst length: 2, 4, 8