EMB08K04G Datasheet | Excelliance MOS

N‐Channel Logic Level Enhancement Mode Field Effect Transistor Product Summary: N‐CH‐Q1 N‐CH‐Q2 BVDSS 40V 40V RDSON (MAX.) 17.5mΩ 8.8mΩ 7.4A 10.5A UIS, Rg 100% Tested Pb‐Free Lead Plating & Halogen Free ABSOLUTE MAXIMUM RATINGS (TA = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS SYMBOL Gate‐Source Voltage Continuous Drain Current Pulsed Drain Current1 TA = 25 °C TA = 70 °C Avalanche Current Avalanche Energy Repetitive Avalanche Energy2 L = 0.1m H, RG=25Ω L = 0.05m H Power Dissipation TA = 25 °C TA = 100 °C Operating Junction & Storage Temperature Range THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL Junction‐to‐Case RJC Junction‐to‐Ambient3 RJA 1Pulse width limited by maximum junction temperature. 2Duty cycle  1％ 362.5°C / W when mounted on a 1 in2 pad of 2 oz copper. VGS ID IDM IAS EAS EAR PD Tj, Tstg TYPICAL LIMITS Q1 Q2 ±20 ±20...