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N‐Channel Logic Level Enhancement Mode Field Effect Transistor
Product Summary:
BVDSS
100V
D
RDSON (MAX.)
500mΩ
ID
1.8A
G
UIS 100% Tested
S
Pb‐Free Lead Plating & Halogen Free
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS
SYMBOL
Gate‐Source Voltage Continuous Drain Current Pulsed Drain Current1
VGS
TA = 25 °C ID
TA = 100 °C
IDM
Power Dissipation
TA = 25 °C TA = 100 °C
Operating Junction & Storage Temperature Range
PD Tj, Tstg
THERMAL RESISTANCE RATINGS THERMAL RESISTANCE
SYMBOL
Junction‐to‐Case
RJC
Junction‐to‐Ambient3
RJA
1Pulse width limited by maximum junction temperature. 2Duty cycle 1％
385°C / W when mounted on a 1 in2 pad of 2 oz copper.
TYPICAL
EMBE0N10P
LIMITS ±20 1.8 1.2 7.2 1.47 0.
EMBE0N10P Datasheet
