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P-Channel Logic Level Enhancement Mode Field Effect Transistor
Product Summary:
D
BVDSS
-20V
RDSON (MAX.)
100mΩ
ID
-3.4A
G
S Pb-Free Lead Plating & Halogen Free
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS
SYMBOL
Gate-Source Voltage
VGS
Continuous Drain Current Pulsed Drain Current1
TA = 25 °C ID
TA = 70 °C
IDM
Power Dissipation
TA = 25 °C TA = 70 °C
Operating Junction & Storage Temperature Range
PD Tj, Tstg
EMFA0P02JS
LIMITS ±12 -3.4 -2.4 -14 1.04 0.66
-55 to 150
UNIT V
A
W °C
THERMAL RESISTANCE RATINGS THERMAL RESISTANCE
SYMBOL
Junction-to-Ambient3
RθJA (T ≤ 10sec) RθJA (Steady State)
1Pulse width limited by maximum junction temperature. 2Duty cycle ≤ 1％ 3The device mounted on a 1 in2 pad of 2 oz copper.
EMFA0P02JS Datasheet
