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P‐Channel Logic Level Enhancement Mode Field Effect Transistor
Product Summary:
D
BVDSS
‐20V
RDSON (MAX.)
100mΩ
ID
‐1.6A
G
S Pb‐Free Lead Plating & Halogen Free
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS
SYMBOL
Gate‐Source Voltage
Continuous Drain Current Pulsed Drain Current1
TA = 25 °C TA = 70 °C
Power Dissipation
TA = 25 °C TA = 70 °C
Operating Junction & Storage Temperature Range
VGS ID IDM PD Tj, Tstg
EMFA0P02M
LIMITS ±12 ‐1.6 ‐1.2 ‐6.4 0.29 0.19
‐55 to 150
UNIT V
A
W °C
THERMAL RESISTANCE RATINGS THERMAL RESISTANCE
SYMBOL
Junction‐to‐Ambient
RJA
Junction‐to‐Lead
RJL
1Pulse width limited by maximum junction temperature. 2Duty cycle 1％
TYPICAL
MAXIMUM 425 320
UNIT °C / W
2012/12/26 p.
EMFA0P02M Datasheet
