Datasheet4U Logo Datasheet4U.com

24C03 - NM24C03

Datasheet Summary

Description

The NM24C02/03 devices are 2048 bits of CMOS non-volatile electrically erasable memory.

These devices conform to all specifications in the I2C™ 2-wire protocol and are designed to minimize device pin count, and simplify PC board layout requirements.

Features

  • s Extended operating voltage 2.7V.
  • 5.5V s 400 kHz clock frequency (F) at 2.7V - 5.5V s 500µA active current typical 10µA standby current typical 1µA standby typical (L) 0.1µA standby typical (LZ) s I2C compatible interface.
  • Provides bidirectional data transfer protocol s Sixteen byte page write mode.
  • Minimizes total write time per byte s Self timed write cycle Typical write cycle time of 6ms s Hardware write protect for upper block (NM24C03 only) s Endurance: 1,000,000.

📥 Download Datasheet

Datasheet preview – 24C03

Datasheet Details

Part number 24C03
Manufacturer Fairchild Semiconductor
File Size 89.69 KB
Description NM24C03
Datasheet download datasheet 24C03 Datasheet
Additional preview pages of the 24C03 datasheet.

📁 Similar Datasheet

  • 24C00 - 128-Bit I2C Bus Serial EEPROM (Microchip)
  • 24C01 - 2-Wire Serial EEPROM (ATMELCorporation)
  • 24C01 - 2-WIRE SERIAL CMOS EEPROM (ISSI)
  • 24C01 - 1K/2K ELECTRICALLY ERASABLE PROGRAMMABLE ROM (Turbo IC)
  • 24C01 - I2C bus EEPROM (STMicroelectronics)
  • 24C016 - 2 Wire Serial CMOS EEPROM (ISSI)
  • 24C01A - 1K/2K/4K 5.0V I2C Serial EEPROMs (MicrochipTechnology)
  • 24C01A - 2-Wire Serial EEPROM (ATMEL)
  • 24C01B - 1K/2K 5.0V I2C Serial EEPROM (MicrochipTechnology)
  • 24C01B1 - ST24C01B1 (STMicroelectronics)
Other Datasheets by Fairchild Semiconductor

Full PDF Text Transcription

Click to expand full text
www.DataSheet4U.net NM24C02/03 – 2048-Bit Standard 2-Wire Bus Interface Serial EEPROM February 1999 NM24C02/03 – 2048-Bit Standard 2-Wire Bus Interface Serial EEPROM General Description The NM24C02/03 devices are 2048 bits of CMOS non-volatile electrically erasable memory. These devices conform to all specifications in the I2C™ 2-wire protocol and are designed to minimize device pin count, and simplify PC board layout requirements. The upper half of the memory of the 24C03 can be disabled (Write Protected) by connecting the WP pin to VCC. This section of memory then becomes unalterable unless WP is switched to VSS.
Published: |