24C03 Datasheet | Fairchild Semiconductor

ription The NM24C02/03 devices are 2048 bits of CMOS non-volatile electrically erasable memory. These devices conform to all specifications in the I2C™ 2-wire protocol and are designed to minimize device pin count, and simplify PC board layout requirements. The upper half of the memory of the 24C03 can be disabled (Write Protected) by connecting the WP pin to VCC. This section of memory then bees unalterable unless WP is switched to VSS. This munications protocol uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master (for example a microprocessor) and the slave EEPROM device(s). In addition, this bus structure allows for a maximum of 16K of EEPROM memory. This is supported by the Fairchild family in 2K, 4K, 8K, and 16K devices, allowing the user to configure the memory as the application requires with any bination of EEPROMs (not to exceed 16K). For devices with densities greater than 16K, a different protocol is used. Refer to 32K or higher densities for additional details. Fairchild EEPROMs are designed and tested for applications requiring high endurance, high reliability and low power consumption. Features s Extended operating voltage 2.7V - 5.5V s 400 k Hz clock frequency (F) at 2.7V - 5.5V s 500µA active current typical 10µA standby current typical 1µA standby typical (L) 0.1µA standby typical (LZ) s I2C patible interface - Provides bidirectional data transfer protocol s Sixteen byte page write mode - Minimizes total write time per byte s Self timed write cycle Typical write cycle time of 6ms s Hardware write protect for upper block (NM24C03 only) s Endurance: 1,000,000 data changes s Data retention greater than 40 years s Packages available: 8-pin DIP, 8-pin SO, and 8-pin TSSOP s Available in three temperature ranges - mercial: 0° to +70°C - Extended (E): -40° to +85C - Automotive (V): -40° to +125°C Block Diagram VCC VSS WP H.V. GENERATION TIMING &CONTROL START STOP LOGIC CONTROL LOGIC SLAVE ADDRESS REGISTER & PARATOR...