Datasheet4U Logo Datasheet4U.com

24C03EN - NM24C03EN

Datasheet Summary

Description

The NM24C02/03 devices are 2048 bits of CMOS non-volatile electrically erasable memory.

These devices conform to all specifications in the Standard IIC 2-wire protocol and are designed to minimize device pin count, and simplify PC board layout requirements.

Features

  • I Extended operating voltage 2.7V.
  • 5.5V I 400 KHz clock frequency (F) at 2.7V - 5.5V I 200µA active current typical 10µA standby current typical 1µA standby current typical (L) 0.1µA standby current typical (LZ) I IIC compatible interface.
  • Provides bi-directional data transfer protocol I Schmitt trigger inputs I Sixteen byte page write mode.
  • Minimizes total write time per byte I Self timed write cycle Typical write cycle time of 6ms I Hardware Write Protect for upper h.

📥 Download Datasheet

Datasheet preview – 24C03EN

Datasheet Details

Part number 24C03EN
Manufacturer Fairchild Semiconductor
File Size 142.53 KB
Description NM24C03EN
Datasheet download datasheet 24C03EN Datasheet
Additional preview pages of the 24C03EN datasheet.

📁 Similar Datasheet

  • 24C00 - 128-Bit I2C Bus Serial EEPROM (Microchip)
  • 24C01 - 2-Wire Serial EEPROM (ATMELCorporation)
  • 24C01 - 2-WIRE SERIAL CMOS EEPROM (ISSI)
  • 24C01 - 1K/2K ELECTRICALLY ERASABLE PROGRAMMABLE ROM (Turbo IC)
  • 24C01 - I2C bus EEPROM (STMicroelectronics)
  • 24C016 - 2 Wire Serial CMOS EEPROM (ISSI)
  • 24C01A - 1K/2K/4K 5.0V I2C Serial EEPROMs (MicrochipTechnology)
  • 24C01A - 2-Wire Serial EEPROM (ATMEL)
  • 24C01B - 1K/2K 5.0V I2C Serial EEPROM (MicrochipTechnology)
  • 24C01B1 - ST24C01B1 (STMicroelectronics)
Other Datasheets by Fairchild Semiconductor

Full PDF Text Transcription

Click to expand full text
NM24C02/03 – 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM February 2000 NM24C02/03 – 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM General Description The NM24C02/03 devices are 2048 bits of CMOS non-volatile electrically erasable memory. These devices conform to all specifications in the Standard IIC 2-wire protocol and are designed to minimize device pin count, and simplify PC board layout requirements. The upper half (upper 1Kbit) of the memory of the NM24C03 can be write protected by connecting the WP pin to VCC. This section of memory then becomes unalterable unless WP is switched to VSS. This communications protocol uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master (for example a microprocessor) and the slave EEPROM device(s).
Published: |