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24C05LN - NM24C05

Datasheet Summary

Description

The NM24C04/05 devices are 4096 bits of CMOS non-volatile electrically erasable memory.

These devices conform to all specifications in the Standard IIC 2-wire protocol and are designed to minimize device pin count, and simplify PC board layout requirements.

Features

  • I Extended operating voltage 2.7V.
  • 5.5V I 400 KHz clock frequency (F) at 2.7V - 5.5V I 200µA active current typical 10µA standby current typical 1µA standby current typical (L) 0.1µA standby current typical (LZ) I IIC compatible interface.
  • Provides bi-directional data transfer protocol I Schmitt trigger inputs I Sixteen byte page write mode.
  • Minimizes total write time per byte I Self timed write cycle Typical write cycle time of 6ms I Hardware Write Protect for upper h.

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Datasheet preview – 24C05LN

Datasheet Details

Part number 24C05LN
Manufacturer Fairchild Semiconductor
File Size 101.65 KB
Description NM24C05
Datasheet download datasheet 24C05LN Datasheet
Additional preview pages of the 24C05LN datasheet.

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Full PDF Text Transcription

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NM24C04/05 – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM NM24C04/05 – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM February 2000 General Description The NM24C04/05 devices are 4096 bits of CMOS non-volatile electrically erasable memory. These devices conform to all specifications in the Standard IIC 2-wire protocol and are designed to minimize device pin count, and simplify PC board layout requirements. The upper half (upper 2Kbit) of the memory of the NM24C05 can be write protected by connecting the WP pin to VCC. This section of memory then becomes unalterable unless WP is switched to VSS. This communications protocol uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master (for example a microprocessor) and the slave EEPROM device(s).
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