74LS164
Description
These 8-bit shift registers feature gated serial inputs and an asynchronous clear. A low logic level at either input inhibits entry of the new data, and resets the first flip-flop to the low level at the next clock pulse, thus providing plete control over ining data.
Key Features
- Specify by appending the suffix letter “X” to the ordering code
- Connection Diagram Function Table Inputs Clear L H H H H Clock X L ↑ ↑ ↑ A X X H L X B X X H X L QA L QA0 H L L Outputs QB L QB0 QAn QAn QAn
- QAn, QGn = The level of QA or QG before the most recent ↑ transition of the clock; indicates a one-bit shift
- © 2000 Fairchild Semiconductor Corporation DS006398 .fairchildsemi
- DM74LS164 Logic Diagram Timing Diagram .fairchildsemi
