74LVTH32244 Datasheet | Fairchild Semiconductor

Description The LVT32244 and LVTH32244 contain thirty-two noninverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble controlled. Individual 3-STATE control inputs can be shorted together for 8-bit, 16-bit, or 32-bit operation. The LVTH32244 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These buffers and line drivers are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT32244 and LVTH32244 are fabricated with an advanced Bi CMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation Features s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH32244), also available without bushold feature (74LVT32244). s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink - 32 m A/+64 m A s ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V s Packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) Ordering Code: Order Number 74LVT32244GX (Note 1) 74LVTH32244GX (Note 1) Package Number BGA96A (Preliminary) BGA96A (Preliminary) Package Description 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [Tape and Reel] 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [Tape and Reel] Note 1: BGA package available in Tape and Reel only. Logic Symbol © 2001 Fairchild Semiconductor Corporation DS500434 .fairchildsemi. Preliminary 74LVT32244 - 74LVTH32244 Connection Diagram Truth Tables Inputs OE1 L L H Inputs OE2 L L H Inputs OE3 L L H (Top Thru View) Inputs OE4 L Description Output Enable Input (Active LOW) Inputs Outputs OE5 L L 5 I0...