74LVTH32373 Datasheet | Fairchild Semiconductor

Description The LVT32373 and LVTH32373 contain thirty-two noninverting latches with 3-STATE outputs and are intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in a high impedance state. The LVTH32373 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These latches are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT32373 and LVTH32373 are fabricated with an advanced Bi CMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation. Features s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH32373), also available without bushold feature (74LVT32373) s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink - 32 m A/+64 m A s ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V s Packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) Ordering Code: Order Number 74LVT32373GX (Note 1) 74LVTH32373GX (Note 1) Package Number BGA96A (Preliminary) BGA96A (Preliminary) Package Description 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] Note 1: BGA package available in Tape and Reel only. Logic Symbol © 2001 Fairchild Semiconductor Corporation DS500548 .fairchildsemi. Preliminary 74LVT32373 - 74LVTH32373 Connection Diagram Pin Descriptions Pin Names OEn LEn I0- I31 O0- O31 Description Output Enable...