SSTV16859 Datasheet | Fairchild Semiconductor

SSTV16859 Dual Output 13-Bit Register with SSTL-2 patible I/O and Reset March 2001 Revised July 2002 SSTV16859 Dual Output 13-Bit Register with SSTL-2 patible I/O and Reset General Description .. The SSTV16859 is a dual output 13-bit register designed for use with 184 and 232 pin DDR-1 memory modules. The device has a differential input clock, SSTL-2 patible data inputs and a LVCMOS patible RESET input. The device has been designed to meet the JEDEC DDR module register specifications. The device has been fabricated on an advanced submicron CMOS process and is designed to operate at power supplies of less than 3.6V’s. Features I pliant with DDR-I registered module specifications I Operates at 2.5V ± 0.2V VDD I SSTL-2 patible input structure I SSTL-2 pliant output structure I Differential SSTL-2 patible clock inputs I Low power mode when device is reset I Industry standard 64 pin TSSOP package I Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) Ordering Code: Order Number SSTV16859G (Note 1)(Note 2) SSTV16859MTD (Note 2) Package Number BGA96A MTD64 Package Description 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Note 1: Ordering code “G” indicates Trays. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2002 Fairchild Semiconductor Corporation DS500414 .fairchildsemi. Connection Diagrams Pin Assignment for TSSOP Pin Descriptions Pin Name Q1A-Q13A Q1B-Q13B D1-D13 RESET CK CK VREF VDDQ VDD NC SSTL-2 patible Register Inputs Asynchronous LVCMOS Reset Input Positive Master Clock Input Negative Master Clock Input Voltage Reference Pin for SSTL level inputs Power Supply Voltage for Output Signals Power Supply Voltage for Inputs Electrically Isolated No Connect Description SSTL-2 patible Register Outputs .. FBGA...