SSTV16857 Datasheet | NXP Semiconductors

FEATURES - Stub-series terminated logic for 2.5 V VDDQ (SSTL_2) - Optimized for DDR (Double Data Rate) SDRAM applications - Inputs patible with JESD8- 9 SSTL_2 specifications. - Flow-through architecture optimizes PCB layout - ESD classification testing is done to JEDEC Standard JESD22. - Latch-up testing is done to JEDEC Standard JESD78, which exceeds 100 m A. .. - Same form, fit, and function as SSTL16877 Protection exceeds 2000 V to HBM per method A114. PIN CONFIGURATION Q1 Q2 GND VDDQ Q3 Q4 Q5 GND VDDQ 1 2 3 4 5 6 7 8 9 48 D1 47 D2 46 GND 45 VCC 44 D3 43 D4 42 D5 41 D6 40 D7 39 CLK- 38 CLK+ 37 VCC 36 GND 35 VREF 34 RESET 33 D8 32 D9 31 D10 30 D11 29 D12 28 VCC 27 GND 26 D13 25 D14 - Full DDR 200/266 solution @ 2.5 V when used with PCKV857 - See SSTV16856 for driver/buffer version with mode select. - Available in TSSOP-48, TVSOP-48 and 56 ball VFBGA packages DESCRIPTION Q6 10 Q7 11 VDDQ 12 GND 13 Q8 14 Q9 15 VDDQ 16 GND 17 Q10 18 Q11 19 Q12 20 VDDQ 21 GND 22 Q13 23 Q14 24 The SSTV16857 is a 14-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V. VDDQ must not exceed VCC. Inputs are SSTL_2 type with VREF normally at 0.5- VDDQ. The outputs support class I which can be used for standard stub-series applications or capacitive loads. Master reset (RESET) asynchronously resets all registers to zero. The SSTV16857 is intended to be incorporated into standard DIMM (Dual In-Line Memory Module) designs defined by JEDEC, such as DDR (Double Data Rate) SDRAM or SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both clock edges (rising and falling), thus doubling the peak bus bandwidth. A DDR DRAM rated at 133 MHz will have a burst rate of 266 MHz. The modules require between 23 and 27 registered control and address lines, so two 14-bit wide devices will be used on each module. The SSTV16857 is intended to be used for SSTL_2 input and output signals. The device data inputs consist of...