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June1996
NDC632P P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package.
Features
-2.7A, -20V. RDS(ON) = 0.14Ω @ VGS = -4.5V RDS(ON) = 0.2Ω @ VGS = -2.7V.