Description
These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology.
Features
- -2.4A, -30V. RDS(ON) = 0.18Ω @ VGS = -4.5V RDS(ON) = 0.11Ω @ VGS = -10V. Proprietary SuperSOTTM-6 package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability. ____________________________________________________________________________________________
4
3
5
2
6
1
Absolute Maximum Ratings
Symbol Parameter VDSS VGSS ID PD Drain-Source Voltage Gate-Sou.
NDC652 Datasheet
