Datasheet4U Logo Datasheet4U.com

MBM29F002TC-55 - 2M (256K x 8) BIT FLASH MEMORY

This page provides the datasheet information for the MBM29F002TC-55, a member of the MBM29F002TC 2M (256K x 8) BIT FLASH MEMORY family.

Datasheet Summary

Features

  • Single 5.0 V read, write, and erase Minimizes system level power requirements.
  • Compatible with JEDEC-standard commands Pinout and software compatible with single-power supply Flash Superior inadvertent write protection.
  • 32-pin TSOP(I) (Package Suffix: PFTN-Normal Bend Type, PFTR-Reverse Bend Type) 32-pin PLCC (Package Suffix: PD).
  • Minimum 100,000 write/erase cycles.
  • High performance 55 ns maximum access time.
  • Sector erase architecture One 16.

📥 Download Datasheet

Datasheet preview – MBM29F002TC-55

Datasheet Details

Part number MBM29F002TC-55
Manufacturer Fujitsu
File Size 461.15 KB
Description 2M (256K x 8) BIT FLASH MEMORY
Datasheet download datasheet MBM29F002TC-55 Datasheet
Additional preview pages of the MBM29F002TC-55 datasheet.

📁 Similar Datasheet

  • MBM29F002TC - 2M (256K x 8) BIT FLASH MEMORY (Fujitsu Media Devices)
  • MBM29F002BC - 2M (256K X 8) BIT (Fujitsu Media Devices)
  • MBM29F004BC - FLASH MEMORY CMOS 4M (512K x 8) BIT (Fujitsu Media Devices)
  • MBM29F004TC - (MBM29F004BC/TC) FLASH MEMORY CMOS 4 M (512 K X 8) BIT (Fujitsu Media Devices)
  • MBM29F016A - 16M (2M x 8) BIT FLASH MEMORY (Fujitsu Media Devices)
  • MBM29F017A - 16M (2M x 8) BIT FLASH MEMORY (Fujitsu Media Devices)
  • MBM29F033C - 32M (4M x 8) BIT FLASH MEMORY (Fujitsu Media Devices)
  • MBM29F040A - FLASH MEMORY 4M 512K x 8 BIT (Fujitsu Media Devices)
  • MBM29F040C - 4M (512K X 8) BIT FLASH MEMORY (Fujitsu Media Devices)
  • MBM29F040C-55 - 4M (512K X 8) BIT FLASH MEMORY (Fujitsu Media Devices)
Other Datasheets by Fujitsu

Full PDF Text Transcription

Click to expand full text
FUJITSU SEMICONDUCTOR DATA SHEET FLASH MEMORY CMOS 2M (256K × 8) BIT DS05-20868-3E MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90 s FEATURES • Single 5.0 V read, write, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Pinout and software compatible with single-power supply Flash Superior inadvertent write protection • 32-pin TSOP(I) (Package Suffix: PFTN-Normal Bend Type, PFTR-Reverse Bend Type) 32-pin PLCC (Package Suffix: PD) • Minimum 100,000 write/erase cycles • High performance 55 ns maximum access time • Sector erase architecture One 16K byte, two 8K bytes, one 32K byte, and three 64K bytes Any combination of sectors can be erased.
Published: |