GS841E18AB Datasheet | GSI Technology

.. GS841E18AT/B-180/166/150/130/100 TQFP, BGA mercial Temp Industrial Temp Features - 3.3 V +10%/- 5% core power supply, 2.5 V or 3.3 V I/O supply - Dual Cycle Deselect (DCD) - Intergrated data parator for Tag RAM application - FT mode pin for flow through or pipeline operation - LBO pin for Linear or Interleave (Pentium TM and X86) Burst mode - Synchronous address, data I/O, and control inputs - Synchronous Data Enable (DE) - Asynchronous Output Enable (OE) - Asynchronous Match Output Enable (MOE) - Byte Write (BWE) and Global Write (GW) operation - Three chip enable signals for easy depth expansion - Internal self-timed write cycle - JTAG Test mode conforms to IEEE standard 1149.1 - JEDEC-standard 100-lead TQFP package and 119-BGA - Pb-Free 100-lead TQFP package available 256K x 18 Sync Cache Tag 180 MHz- 100 MHz 3.3 V VDD 3.3 V and 2.5 V I/O Output registers and the Match output register are provided and controlled by the FT mode pin (Pin 14). Through use of the FT mode pin, I/O registers can be programmed to perform pipeline or flow through operation. Flow Through mode reduces latency. Byte write operation is performed by using Byte Write Enable (BWE) input bined with two individual byte write signals BW1-2. In addition, Global Write (GW) is available for writing all bytes at one time. pare cycles begin as a read cycle with output disabled so that pare data can be loaded into the data input register. The parator pares the read data with the registered input data and a match signal is generated. The match output can be either in Pipeline or Flow Through modes controlled by the FT signal. Low power (Standby mode) is attained through the assertion of the ZZ signal, or by stopping the clock (CLK). Memory data is retained during Standby mode. JTAG boundary scan interface is provided using IEEE standard 1149.1 protocol. Four pins- Test Data In (TDI), Test Data Out (TDO), Test Clock (TCK) and Test Mode Select (TMS)- are used to...