HD74HCT137 Datasheet | Hitachi Semiconductor

Description The HD74HCT137 implements a three-to-eight line decoder with latches on the three address inputs. When GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As long as GL remains high no address changes will be recognized. Output enable controls, G1 and G2, control the state of the outputs independently of the select or latch-enable inputs. All of the outputs are high unless G1 is high and G2 is low. The HD74HCT137 is ideally suited for the implementation of glitchfree decoders in stored-address applications in bus oriented systems. Features - - - - - - LSTTL Output Logic Level patibility as well as CMOS Output patibility High Speed Operation: tpd (A, B, C to Y) = 18 ns typ (C L = 50 p F) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 4.5 to 5.5 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Inputs Enable GL X X L L L L L L L L H G1 X L H H H H H H H H H G2 H X L L L L L L L L L Select C X X L L L L H H H H X B X X L L H H L L H H X A X X L H L H L H L H X Outputs Y0 H H L H H H H H H H Y1 H H H L H H H H H H Y2 H H H H L H H H H H Y3 H H H H H L H H H H Y4 H H H H H H L H H H Y5 H H H H H H H L H H Y6 H H H H H H H H L H Y7 H H H H H H H H H L Output Corresponding to stored address L; all others H Pin Arrangement A 1 B 2 C 3 GL 4 G2 5 G1 6 Y7 7 GND 8 B C GL G2 G1 Y7 Y6 A Y0 Y1 Y2 Y3 Y4 Y5 16 VCC 15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6 (Top view) Logic Diagram CK CK CK Y0 Y1 B Y2 Y3 Y4 Y5 Y6 Y7 G2 G1 DC Characteristics Ta = 25°C Item Input voltage Symbol VIH VIL Output voltage VOH Ta = - 40 to +85°C Max - 0.8 - - 0.1 0.33 ±1.0 40 µA µA V Unit V V V Test Conditions VCC (V) 4.5 to 5.5 4.5 to 5.5 4.5 4.5 4.5 4.5 5.5 5.5 Vin = VIH or VIL I OH = - 20 µA I OH = - 4 m A Vin = VIH or VIL I OL = 20 µA I OL = 4 m A Vin = VCC or GND Vin = VCC or GND, Iout = 0...