HM62V8512CI Datasheet | Hitachi Semiconductor

Description The Hitachi HM62V8512CI is a 4-Mbit static RAM organized 512-kword × 8-bit. HM62V8512CI Series has realized higher density, higher performance and low power consumption by employing CMOS process technology (6-transistor memory cell). The HM62V8512CI Series offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It is packaged in standard 32-pin TSOP II. Features - Single 3.0 V supply: 2.7 V to 3.6 V - Access time: 70 ns (max) - Power dissipation  Active: 6.0 m W/MHz (typ)  Standby: 2.4 µW (typ) - pletely static memory. No clock or timing strobe required - Equal access and cycle times - mon data input and output: Three state output - Directly LV-TTL patible: All inputs and outputs - Battery backup operation - Operating temperature: - 40 to +85˚C Ordering Information Type No. HM62V8512CLTTI-7 Access time 70 ns Package 400-mil 32-pin plastic TSOP II (TTP-32D) HM62V8512CI Series Pin Arrangement 32-pin TSOP A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 Pin Description Pin name A0 to A18 I/O0 to I/O7 CS OE WE VCC VSS Function Address input Data input/output Chip select Output enable Write enable Power supply Ground HM62V8512CI Series Block Diagram LSB V CC V SS - - - - - MSB A11 A9 A8 A15 A18 A10 A13 A17 A16 A14 A12 Row Decoder Memory Matrix 2,048 × 2,048 I/O0 Input Data Control I/O7 - - Column I/O Column Decoder - - LSB A3 A2A1A0 A4 A5 A6 A7 MSB - - CS WE OE Timing Pulse Generator Read/Write...