HM62W4100H Datasheet | Hitachi Semiconductor

Description The HM62W4100H is a 4-Mbit high speed static RAM organized 1-Mword × 4-bit. It has realized high speed access time by employing CMOS process (4-transistor + 2-poly resistor memory cell) and high speed circuit designing technology. It is most appropriate for the application which requires high speed and high density memory, such as cache and buffer memory in system. The HM62W4100H is packaged in 400-mil 32-pin SOJ for high density surface mounting. Features - Single supply : 3.3 V ± 0.3 V - Access time 12/15 ns (max) - pletely static memory  No clock or timing strobe required - Equal access and cycle times - Directly TTL patible  All inputs and outputs - Operating current : 180/160 m A (max) - TTL standby current : 60/50 m A (max) - CMOS standby current : 5 m A (max) : 1 m A (max) (L-version) - Data retension current : 0.6 m A (max) (L-version) - Data retension voltage: 2 V (min) (L-version) - Center VCC and VSS type pinout HM62W4100H Series Ordering Information Type No. HM62W4100HJP-12 HM62W4100HJP-15 HM62W4100HLJP-12 HM62W4100HLJP-15 Access time 12 ns 15 ns 12 ns 15 ns Package 400-mil 32-pin plastic SOJ (CP-32DB) Pin Arrangement HM62W4100HJP/HLJP Series A0 A1 A2 A3 A4 CS I/O1 VCC VSS I/O2 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A19 A18 A17 A16 A15 OE I/O4 VSS VCC I/O3 A14 A13 A12 A11 A10 NC HM62W4100H Series Pin Description Pin name A0 to A19 I/O1 to I/O4 CS OE WE VCC VSS NC Function Address input Data input/output Chip select Output enable Write enable Power supply Ground No connection Block Diagram (LSB) A1 A17 A7 A11 A16 A2 A6 A5 (MSB) VCC Row decoder Memory matrix 256 rows × 16 columns × 256 blocks × 4 bit (4,194,304 bits) VSS CS I/O1 . . . I/O4 Column I/O Input data control Column decoder CS A10 A8 A9 A19 A12 A13 A14 A0 A18 A15 A3 A4 WE CS (LSB) (MSB) OE CS HM62W4100H Series Operation Table CS H L L L L Note: OE × H L H L ×: H or L WE × H H L L Mode Standby...