HM62W8512B Datasheet | Hitachi Semiconductor

Description The Hitachi HM62W8512B is a 4-Mbit static RAM organized 512-kword × 8-bit. It realizes higher density, higher performance and low power consumption by employing 0.35 µm Hi-CMOS process technology. The device, packaged in a 525-mil SOP (foot print pitch width) or 400-mil TSOP TYPE II is available for high density mounting. The HM62W8512B is suitable for battery backup system. Features - Single 3.3 V supply: 3.3 V ± 0.3 V - Access time: 55/70 ns (max) - Power dissipation  Active: 16.5 m W/MHz (typ)  Standby: 3.3 µW (typ) - pletely static memory. No clock or timing strobe required - Equal access and cycle times - mon data input and output: Three state output - Directly LV-TTL patible: All inputs and outputs - Battery backup operation HM62W8512B Series Ordering Information Type No. HM62W8512BLFP-5 HM62W8512BLFP-7 Access time 55 ns 70 ns Package 525-mil 32-pin plastic SOP (FP-32D) HM62W8512BLFP-5SL 55 ns HM62W8512BLFP-7SL 70 ns HM62W8512BLFP-5UL 55 ns HM62W8512BLFP-7UL 70 ns HM62W8512BLTT-5 HM62W8512BLTT-7 HM62W8512BLTT-5SL HM62W8512BLTT-7SL 55 ns 70 ns 55 ns 70 ns 400-mil 32-pin plastic TSOP II (TTP-32D) HM62W8512BLTT-5UL 55 ns HM62W8512BLTT-7UL 70 ns HM62W8512BLRR-5 HM62W8512BLRR-7 55 ns 70 ns 400-mil 32-pin plastic TSOP II reverse (TTP-32DR) HM62W8512BLRR-5SL 55 ns HM62W8512BLRR-7SL 70 ns HM62W8512BLRR-5UL 55 ns HM62W8512BLRR-7UL 70 ns HM62W8512B Series Pin Arrangement HM62W8512BLFP Series A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view) HM62W8512BLRR Series VCC A15 A17 WE A13 A8 A9 A11 OE A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 (Top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1...