HX6256 - 32K x 8 Static RAM

Typ 5.0 25 Max 5.5 125 VDD+0.3 50 Units V °C V ms CAPACITANCE (1) Symbol CI CO Parameter Input Capacitance Output Capacitance Typical (1) 5 7 Worst Case Min Max 7 9 Units pF pF Test Conditions VI=VDD or VSS, f=1 MHz VIO=VDD or VSS, f=1 MHz (1) This parameter is tested during initial design charact

• include tungsten via plugs, Honeywell’s proprietary SHARP planarization process, and a lightly doped drain (LDD) structure for improved short channel reliability. A 7 transistor (7T) memory cell is used for superior single event upset hardening, while three layer metal power bussing and the low collection volume SOI substrate provide improved dose rate hardening.