HY57V643220D Datasheet | SK Hynix

description of the package type in PACKAGE DIMENSION 1.Corrected : Lead range tolerance (Page : 13) History Draft Date May. 2004 July 2004 Sep. 2004 Sep. 2005 Remark Preliminary . Data Shee This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4 / Sep. 2005 1 . . Data Sheet 4 U . .. HY57V643220D(L/S)T(P) Series 4Banks x 512K x 32bits Synchronous DRAM DESCRIPTION The Hynix HY57V643220D(L/S)T(P) series is a 67,108,864bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY57V643220D(L/S)T(P) is organized as 4banks of 524,228x32. HY57V643220D(L/S)T(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are patible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control mand (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate mand or can be interrupted and replaced by a new burst read or write mand on any cycle. (This pipelined design is not restricted by a '2N' rule) FEATURES - - - - - - Voltage : VDD, VDDQ 3.3V supply voltage All device pins are patible with LVTTL interface JEDEC standard 400mil 86pin TSOP-II with 0.5mm of pin pitch - - - Auto refresh and self refresh 4096 Refresh cycles / 64ms Programmable Burst Length and Burst Type et4U. - 1, 2, 4, 8 or full page for Sequential Burst All inputs and outputs referenced to positive edge of . system clock - 1, 2, 4 or 8 for Interleave Burst Data mask...