HY5DU56822DTP
description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1 /May 2004
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HY5DU56422D(L)TP HY5DU56822D(L)TP HY5DU561622D(L)TP DESCRIPTION
PRELIMINARY
The Hynix HY5DU56422D(L)TP, HY5DU56822D(L)TP and HY5DU561622(L)TP are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. The Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are patible with SSTL_2.
FEATURES...
