HY5V62CF Datasheet | SK Hynix

DESCRIPTION The Hynix HY5V62C is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY5V62C is organized as 4banks of 524,288x32. HY5V62C is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are patible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control mand (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate mand or can be interrupted and replaced by a new burst read or write mand on any cycle. (This pipelined design is not restricted by a `2N` rule.) FEATURES - - - - JEDEC standard 3.3V power supply All device pins are patible with LVTTL interface 90Ball FBGA with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by DQM0,1,2 and 3 - - Internal four banks operation - Burst Read Single Write operation Programmable CAS Latency ; 2, 3 Clocks - - - Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst - ORDERING INFORMATION Part No. HY5V62CF-7 HY5V62CF-S Clock Frequency 143MHz Power Normal Organization 4Banks x 512Kbits x32 Interface LVTTL Package 90Ball FBGA 100MHz This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/Nov. 01 .. PIN CONFIGURATION 1 A D Q 26 D Q 24 VSS VDD D...